Electrical circuits are often susceptible to damage by electrostatic discharge (ESD) currents resulting from unintended contacts with sources of excess electric charge. For example, a user charged with static electricity can discharge ESD currents into an unprotected circuit at potentials of kilovolts. Such ESD currents can be particularly harmful to circuits designed for low voltage applications.
Various techniques have been developed to reduce the potential damage caused by ESD currents. For example, FIG. 1 illustrates a cross-sectional view of a known electrostatic protection device design. As set forth in FIG. 1, an NMOS transistor 100 is provided on a p-doped substrate 150 and includes an n-doped drain region 110, an n-doped source region 120, and a conductive gate 130 isolated from substrate 150 by a gate oxide 135.
An input/output (I/O) pad 160 couples to drain region 110. A voltage source 175 coupled to pad 160 models the effect of a user charged with static electricity. The protective effect of NMOS transistor 100 with regard to voltage source 175 depends upon a “snapback” effect. In this effect, the high voltage from voltage source 175 induces an avalanche breakdown on the reverse-biased junction between drain region 110 and substrate 150. As a result, positive charge will accumulate in substrate 150 such that the junction between substrate 150 and source region 120 becomes forward-biased. In this fashion, a parasitic NPN bipolar transistor 180 (formed from drain region 110, substrate 150, and source region 120) conducts current from drain region 110 to source region 120 as a result of static electricity charging pad 160. In turn, because source region 120 and gate 130 are grounded, a channel 140 is induced in substrate 150 between drain region 110 and source region 120. In this fashion, current is rapidly drained from voltage source 175 into ground, thereby protecting the circuitry (not illustrated) that couples to pad 160.
Although NMOS transistor 100 thus functions as an ESD protection device, problems arise should pad 160 be coupled to an external DC voltage source (in contrast to the transient voltage source 175 arising from a static electricity charge). The DC voltage can overwhelm the thin gate oxide 135 found in today's smaller transistors. For example, in a 0.35 micron CMOS process, gate oxide 135 can only support a potential of 3.3 volts between gate 130 and substrate 150. Thus, should a relatively high DC voltage source such as 12 volts be coupled to pad 160, gate oxide 135 will fail.
An ESD protection approach that can withstand such relatively high voltages at pad 160 involves the use of a stacked circuit design in which several (e.g., three) MOS transistors are connected in series to spread the high voltage and associated stress across the several transistors. However, this approach can require increased chip area for implementation, and is complicated by the need for additional transistors.
Accordingly, there is a need for an improved approach to ESD protection that permits the handling of relatively-high DC voltages at the protected I/O pad without incurring excessive chip area demands.